LVDS & CML Solutions

Select

LVDS & CML Product Tables:

• Crosspoints
• Equalizers/Signal Conditioning
• Fanout/Distribution
• LVDS Drivers & Receivers
• M-LVDS/B-LVDS Drivers & Receivers
• Mux-Buffers
• Repeaters

SerDes - Data Interface

• Embedded Clock SerDes
• Parallel Clock SerDes - Channel Link

SerDes - Displays and Imaging Interface

• FPD-Link II (Embedded Clock LVDS)
• FPD-Link/Open LDI LVDS

Serial Digital Interface (SMPTE)

• Deserializers
• Serializers
• Cable Drivers
• Equalizers
• Reclockers
• Switching Conditioning

Other Related Products

• SDI/Broadcast Video
• Ethernet
• UARTS
• RS-485 / RS-422/423 / RS-232
• Displays
• System Test (JTAG)
• Clock & Timing
• Phase Locked Loops (PLL)
• Wireless Basestation
• A/D Converters (ADCs)

Design

LVDS & CML Design Resources:

• LVDS Owner's Manual (4^th Ed)
  Completely updated for 2008!
  Explains LVDS, CML, signal conditioning, and much more…
• Design Guides
• LVDS Design Resources
• Evaluation Boards
• Transmission Line RAPIDESIGNER Slide Rule
• LVDS Technical Support

LVDS & CML Application Notes:

• Application Notes - Interface
• Application Notes - FPD Link/OpenLDI

LVDS & CML Articles

• Using a step response test is used to characterize a digital communication channel, Dr. Howard Johnson
  • Part 1: Step Response Test
  • Part 2: Confirm the Diagnosis
• How to tell if your interconnect has adequate bandwidth, Dr. Howard Johnson

LVDS & CML Models:

• IBIS (I/O Simulation)
• BSDL (JTAG)

Press Releases

Links to Industry Standards